Pre-RFC: Allow per-thread access to system counter on Aarch64

Currently the default compile does not allow a thread to access the system counter register on ARM.

There is a compile option that does allow threads to account the counter (all threads).

It would be preferable if this was not an all-or-nothing option.

Specifically, it should be possible to enable this on a per-thread basis.

I don’t know exactly what the interface should be. Perhaps an architecture specific TimerControl object, which allows for enabling / disabling timer access for a given TCB.

This would require storing at least another bit in each TCB, and additionally another register to be updated on context switch.

This is not urgent for my use cases, but flagging it for future.

I agree that we will need to allow this register access to be controlled per-thread. Given that there are several machine registers that can be enabled/disabled for user mode by the kernel in this way and their use doesn’t affect the kernel’s core functionality, this new capability type should ideally allow per-register, per-thread access control configuration. IE have scope for managing access to more registers than the timer registers as well.