# Suggestion: move L1\_CACHE\_LINE\_SIZE definition

**URL:** <https://sel4.discourse.group/t/suggestion-move-l1-cache-line-size-definition/98>\
**Category:** seL4 kernel\
**Tags:** suggestion, arm\
**Created:** [July 1, 2019, 2:04am UTC](https://sel4.discourse.group/t/suggestion-move-l1-cache-line-size-definition/98 "2019-07-01T02:04:20Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![anna.lyons](https://yyz2.discourse-cdn.com/free1/user_avatar/sel4.discourse.group/anna.lyons/32/4_2.png) [@anna.lyons](https://sel4.discourse.group/u/anna.lyons)\
**Post date:** [July 1, 2019, 2:04am UTC](https://sel4.discourse.group/t/suggestion-move-l1-cache-line-size-definition/98/1 "2019-07-01T02:04:20Z")

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Currently the constant `L1_CACHE_LINE_SIZE` (for arm) is defined in two places [1,2]:  
[1] [https://github.com/seL4/seL4/blob/master/include/arch/arm/arch/32/mode/machine/hardware.h](https://github.com/seL4/seL4/blob/master/include/arch/arm/arch/32/mode/machine/hardware.h)  
[2] [https://github.com/seL4/seL4/blob/master/include/arch/arm/arch/64/mode/machine/hardware.h](https://github.com/seL4/seL4/blob/master/include/arch/arm/arch/64/mode/machine/hardware.h)

Can we move it to be generated as either:

- part of platform\_gen.h
- or as a new per-cpu family header?

I’d like to define this, and other CPU related settings, in a single place as I need to define the constant for a new CPU family that is unlikely to be merged to master (as the device tree is proprietary) and I’d prefer to keep the patches.

Thoughts? I’m happy to implement it and put a PR up but I’d like it to be consistent with the current direction of configuration in the kernel. cc @kent.mcleod

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<div class="post-metadata">

**Author:** ![kent.mcleod](https://avatars.discourse-cdn.com/v4/letter/k/7ab992/32.png) [@kent.mcleod](https://sel4.discourse.group/u/kent.mcleod)\
**Post date:** [July 1, 2019, 3:48am UTC](https://sel4.discourse.group/t/suggestion-move-l1-cache-line-size-definition/98/2 "2019-07-01T03:48:18Z")

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Could you do something like?:

```auto
if(KernelArmCortexA57)
 config_set(KernelL1CacheLineSizeBits L1_CACHE_LINE_SIZE_BITS 6)
elseif(...)
 config_set(KernelL1CacheLineSizeBits L1_CACHE_LINE_SIZE_BITS 6)
...
endif()

```

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<div class="post-metadata">

**Author:** ![anna.lyons](https://yyz2.discourse-cdn.com/free1/user_avatar/sel4.discourse.group/anna.lyons/32/4_2.png) [@anna.lyons](https://sel4.discourse.group/u/anna.lyons)\
**Post date:** [July 1, 2019, 5:45am UTC](https://sel4.discourse.group/t/suggestion-move-l1-cache-line-size-definition/98/3 "2019-07-01T05:45:36Z")

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cool I’ve put up a PR here [https://github.com/seL4/seL4/pull/134](https://github.com/seL4/seL4/pull/134)