Issue with seL4 & ARMv8 config for MMU

Misbah · February 26, 2025, 1:33pm

#pragma once

#define PHYS_BASE_RAW 0x80000000

#ifndef ASSEMBLER

#include <config.h>
#include <mode/hardware.h> /* for KDEV_BASE /
#include <linker.h> / for BOOT_RODATA /
#include <basic_types.h> / for p_region_t, kernel_frame_t (arch/types.h) */

/* Wrap raw physBase location constant to give it a symbolic name in C that’s

visible to verification. This is necessary as there are no real constants
in C except enums, and enums constants must fit in an int.
*/
static inline CONST word_t physBase(void)
{
return PHYS_BASE_RAW;
}

/* INTERRUPTS /
/ INTERRUPT_VGIC_MAINTENANCE generated from /soc/interrupt-controller@50800000 /
#define INTERRUPT_VGIC_MAINTENANCE 25
/ INTERRUPT_VTIMER_EVENT generated from /timer /
#define INTERRUPT_VTIMER_EVENT 27
/ KERNEL_TIMER_IRQ generated from /timer /
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
#define KERNEL_TIMER_IRQ 26
#else
#define KERNEL_TIMER_IRQ 27
#endif / CONFIG_ARM_HYPERVISOR_SUPPORT /
/ KERNEL DEVICES */
#define UART_PPTR (KDEV_BASE + 0x0)
#define GICD_PPTR (KDEV_BASE + 0x1000)
#define GICR_PPTR (KDEV_BASE + 0x11000)

static const kernel_frame_t BOOT_RODATA kernel_device_frames = {
#ifdef CONFIG_PRINTING
/* /soc/serial@401c8000 /
{
.paddr = 0x401c8000,
.pptr = UART_PPTR,
.armExecuteNever = true,
.userAvailable = true
},
#endif / CONFIG_PRINTING /
/ /soc/interrupt-controller@50800000 /
{
.paddr = 0x50800000,
.pptr = GICD_PPTR,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50801000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0x2000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50802000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0x3000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50803000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0x4000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50804000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0x5000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50805000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0x6000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50806000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0x7000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50807000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0x8000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50808000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0x9000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50809000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0xa000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5080a000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0xb000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5080b000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0xc000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5080c000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0xd000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5080d000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0xe000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5080e000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0xf000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5080f000,
/ contains GICD_PPTR /
.pptr = KDEV_BASE + 0x10000,
.armExecuteNever = true,
.userAvailable = false
},
/ /soc/interrupt-controller@50800000 /
{
.paddr = 0x50900000,
.pptr = GICR_PPTR,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50901000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x12000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50902000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x13000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50903000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x14000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50904000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x15000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50905000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x16000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50906000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x17000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50907000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x18000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50908000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x19000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50909000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x1a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5090a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x1b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5090b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x1c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5090c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x1d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5090d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x1e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5090e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x1f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5090f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x20000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50910000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x21000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50911000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x22000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50912000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x23000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50913000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x24000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50914000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x25000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50915000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x26000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50916000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x27000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50917000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x28000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50918000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x29000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50919000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x2a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5091a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x2b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5091b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x2c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5091c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x2d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5091d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x2e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5091e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x2f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5091f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x30000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50920000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x31000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50921000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x32000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50922000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x33000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50923000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x34000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50924000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x35000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50925000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x36000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50926000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x37000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50927000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x38000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50928000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x39000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50929000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x3a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5092a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x3b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5092b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x3c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5092c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x3d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5092d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x3e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5092e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x3f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5092f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x40000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50930000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x41000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50931000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x42000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50932000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x43000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50933000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x44000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50934000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x45000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50935000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x46000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50936000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x47000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50937000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x48000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50938000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x49000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50939000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x4a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5093a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x4b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5093b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x4c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5093c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x4d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5093d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x4e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5093e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x4f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5093f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x50000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50940000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x51000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50941000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x52000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50942000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x53000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50943000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x54000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50944000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x55000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50945000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x56000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50946000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x57000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50947000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x58000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50948000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x59000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50949000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x5a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5094a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x5b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5094b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x5c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5094c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x5d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5094d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x5e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5094e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x5f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5094f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x60000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50950000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x61000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50951000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x62000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50952000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x63000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50953000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x64000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50954000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x65000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50955000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x66000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50956000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x67000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50957000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x68000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50958000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x69000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50959000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x6a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5095a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x6b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5095b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x6c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5095c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x6d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5095d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x6e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5095e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x6f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5095f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x70000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50960000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x71000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50961000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x72000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50962000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x73000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50963000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x74000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50964000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x75000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50965000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x76000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50966000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x77000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50967000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x78000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50968000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x79000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50969000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x7a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5096a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x7b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5096b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x7c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5096c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x7d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5096d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x7e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5096e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x7f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5096f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x80000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50970000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x81000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50971000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x82000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50972000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x83000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50973000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x84000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50974000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x85000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50975000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x86000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50976000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x87000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50977000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x88000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50978000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x89000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50979000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x8a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5097a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x8b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5097b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x8c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5097c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x8d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5097d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x8e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5097e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x8f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5097f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x90000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50980000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x91000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50981000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x92000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50982000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x93000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50983000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x94000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50984000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x95000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50985000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x96000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50986000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x97000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50987000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x98000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50988000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x99000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50989000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x9a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5098a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x9b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5098b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x9c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5098c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x9d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5098d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x9e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5098e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x9f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5098f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xa0000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50990000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xa1000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50991000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xa2000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50992000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xa3000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50993000,
/ contains GICR_PPTR */
.pptr = KDEV_BASE + 0xa4000,
.armExecuteNever = true,
.userAvailable = false
},

Misbah · February 26, 2025, 1:34pm

{
.paddr = 0x50994000,
/* contains GICR_PPTR /
.pptr = KDEV_BASE + 0xa5000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50995000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xa6000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50996000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xa7000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50997000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xa8000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50998000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xa9000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x50999000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xaa000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5099a000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xab000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5099b000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xac000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5099c000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xad000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5099d000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xae000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5099e000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xaf000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x5099f000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb0000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a0000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb1000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a1000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb2000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a2000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb3000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a3000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb4000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a4000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb5000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a5000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb6000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a6000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb7000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a7000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb8000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a8000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xb9000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509a9000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xba000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509aa000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xbb000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ab000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xbc000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ac000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xbd000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ad000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xbe000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ae000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xbf000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509af000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc0000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b0000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc1000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b1000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc2000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b2000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc3000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b3000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc4000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b4000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc5000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b5000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc6000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b6000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc7000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b7000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc8000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b8000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xc9000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509b9000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xca000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ba000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xcb000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509bb000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xcc000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509bc000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xcd000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509bd000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xce000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509be000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xcf000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509bf000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd0000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c0000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd1000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c1000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd2000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c2000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd3000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c3000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd4000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c4000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd5000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c5000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd6000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c6000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd7000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c7000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd8000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c8000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xd9000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509c9000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xda000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ca000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xdb000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509cb000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xdc000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509cc000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xdd000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509cd000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xde000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ce000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xdf000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509cf000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe0000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d0000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe1000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d1000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe2000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d2000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe3000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d3000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe4000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d4000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe5000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d5000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe6000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d6000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe7000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d7000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe8000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d8000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xe9000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509d9000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xea000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509da000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xeb000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509db000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xec000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509dc000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xed000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509dd000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xee000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509de000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xef000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509df000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf0000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e0000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf1000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e1000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf2000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e2000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf3000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e3000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf4000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e4000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf5000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e5000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf6000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e6000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf7000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e7000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf8000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e8000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xf9000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509e9000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xfa000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ea000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xfb000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509eb000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xfc000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ec000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xfd000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ed000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xfe000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ee000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0xff000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ef000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x100000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f0000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x101000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f1000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x102000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f2000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x103000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f3000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x104000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f4000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x105000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f5000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x106000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f6000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x107000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f7000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x108000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f8000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x109000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509f9000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x10a000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509fa000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x10b000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509fb000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x10c000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509fc000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x10d000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509fd000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x10e000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509fe000,
/ contains GICR_PPTR /
.pptr = KDEV_BASE + 0x10f000,
.armExecuteNever = true,
.userAvailable = false
},
{
.paddr = 0x509ff000,
/ contains GICR_PPTR */
.pptr = KDEV_BASE + 0x110000,
.armExecuteNever = true,
.userAvailable = false
},
};

/* Elements in kernel_device_frames may be enabled in specific configurations

only, but the ARRAY_SIZE() macro will automatically take care of this.
However, one corner case remains unsolved where all elements are disabled
and this becomes an empty array effectively. Then the C parser used in the
formal verification process will fail, because it follows the strict C rules
which do not allow empty arrays. Luckily, we have not met this case yet…
*/
#define NUM_KERNEL_DEVICE_FRAMES ARRAY_SIZE(kernel_device_frames)

/* PHYSICAL MEMORY /
static const p_region_t BOOT_RODATA avail_p_regs[] = {
/ /memory@80000000 /
{
.start = 0x80000000,
.end = 0x83200000
},
/ /memory@80000000 /
{
.start = 0x835e0000,
.end = 0x84000000
},
/ /memory@80000000 */
{
.start = 0x84080000,
.end = 0xc0000000
},
};

#endif /* !ASSEMBLER */

kent-mcleod2 · February 26, 2025, 7:57pm

Ok, what about the output of bdinfo from u-boot?

Sometimes when some arm firmware like atf or optee dynamically reserve memory and protect it from the non-secure world these regions aren’t declared in the device tree used to build the kernel.

Misbah · February 27, 2025, 6:24am

Please find the output of the same as below:

=> bdinfo
boot_params = 0x0000000000000000
DRAM bank = 0x0000000000000000
→ start = 0x0000000080000000
→ size = 0x0000000080000000
DRAM bank = 0x0000000000000001
→ start = 0x0000000880000000
→ size = 0x0000000060000000
flashstart = 0x0000000000000000
flashsize = 0x0000000000000000
flashoffset = 0x0000000000000000
baudrate = 115200 bps
relocaddr = 0x00000000ffff0000
reloc off = 0x0000000000000000
Build = 64-bit
current eth = ethernet@4033c000
ethaddr = ea:a2:79:84:08:08
IP addr = 10.0.0.100
fdt_blob = 0x00000000ff891000
new_fdt = 0x00000000ffbe44e0
fdt_size = 0x00000000000098a0
lmb_dump_all:
memory.cnt = 0x2
memory[0] [0x80000000-0xffffffff], 0x80000000 bytes flags: 0
memory[1] [0x880000000-0x8dfffffff], 0x60000000 bytes flags: 0
reserved.cnt = 0x8
reserved[0] [0x34500000-0x3450047f], 0x00000480 bytes flags: 4
reserved[1] [0x83400000-0x83407fff], 0x00008000 bytes flags: 4
reserved[2] [0x84000000-0x84ffffff], 0x01000000 bytes flags: 4
reserved[3] [0xc0000000-0xc07fffff], 0x00800000 bytes flags: 4
reserved[4] [0xd0000000-0xd00000ff], 0x00000100 bytes flags: 4
reserved[5] [0xff600000-0xff7fffff], 0x00200000 bytes flags: 4
reserved[6] [0xff8a0000-0xff9cbf6f], 0x0012bf70 bytes flags: 0
reserved[7] [0xffbdfef0-0xffffffff], 0x00420110 bytes flags: 0
devicetree = board
arch_number = 0x0000000000000000
TLB addr = 0x00000000ffff0000
irq_sp = 0x00000000ffbe44d0
sp start = 0x00000000ffbe44d0
Early malloc usage: 26688 / 40000
=>

kent-mcleod2 · February 27, 2025, 6:54am

One thing it appears that there’s a memory range that uboot is marking as reserved, but the seL4 kernel tool thinks is not reserved: [0x84080000-0x84ffffff]

/ /memory@80000000 */
{
.start = 0x84080000,
.end = 0xc0000000
},

That would be the first thing to try and resolve.

The next thing to try is to find a large continuous region of DRAM that’s available: eg [0x85000000-0xbfffffff] and declare memory@80000000 as that region inside the kernel’s device tree overlay.

The other thing is to make sure that the elfloader is being loaded to the memory address that it expects because it’s not compiled to be relocatable.

Misbah · February 27, 2025, 11:29am

I have made the changes as suggested, but still the issue persist.
Below are the details of the changes done for your reference:

DTS file change as->

reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;

            shm@c0000000 {
                    compatible = "nxp,s32cc-shm";
                    reg = <0x00 0xc0000000 0x00 0x400000>;
                    no-map;
                    phandle = <0x2c>;
            };

            shm@c0400000 {
                    compatible = "nxp,s32cc-shm";
                    reg = <0x00 0xc0400000 0x00 0x400000>;
                    no-map;
                    phandle = <0x30>;
            };

            shm@d0000000 {
                    compatible = "arm,scmi-shmem";
                    reg = <0x00 0xd0000000 0x00 0x100>;
                    no-map;
                    phandle = <0x02>;
            };

            shm@84000000 {
                    compatible = "nxp,s32cc-hse-rmem";
                    reg = <0x00 0x84000000 0x00 0x1000000>;
                    no-map;
                    phandle = <0x1d>;
            };

            /*pfebufs@34000000 {
                    compatible = "nxp,s32g-pfe-bmu2-pool";
                    reg = <0x00 0x34000000 0x00 0x80000>;
                    no-map;
                    status = "okay";
                    phandle = <0x32>;
            };

            pfebufs@34080000 {
                    compatible = "nxp,s32g-pfe-rt-pool";
                    reg = <0x00 0x34080000 0x00 0x20000>;
                    no-map;
                    status = "okay";
                    phandle = <0x33>;
            };
           pfebufs@83200000 {
                    compatible = "shared-dma-pool";
                    reg = <0x00 0x83200000 0x00 0x3e0000>;
                    no-map;
                    status = "okay";
                    phandle = <0x34>;
            };

            pfebufs@835e0000 {
                    compatible = "nxp,s32g-pfe-bdr-pool";
                    reg = <0x00 0x835e0000 0x00 0x20000>;
                    status = "okay";
                    phandle = <0x35>;
            };

            scst-mem@D0400000 {
                    reg = <0x00 0xd0400000 0x00 0x100000>;
                    no-map;
                    status = "okay";
            };*/

    };

Overlay file change as →

/ {
memory@80000000 {
device_type = “memory”;
reg = < 0x00 0x80000000 0x00 0x80000000 >,
<0x00000008 0x80000000 0x00000000 0x60000000>;
};
chosen {
seL4,elfloader-devices =
“serial0”,
&{/firmware/psci},
&{/timer};

            seL4,kernel-devices =
                    "serial0",

&{/soc/interrupt-controller@50800000},
&{/timer};
};
memory@80000000 {
reg = <0x0 0x85000000 0x0 0x60000000>;
};
reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;

            reserved1@34500000 {
                    reg = <0x00 0x34500000 0x00 0x480>;
                    no-map;
                    status = "okay";
            };
            reserved2@83400000 {
                    reg = <0x00 0x83400000 0x00 0x8000>;
                    no-map;
                    status = "okay";
            };
           reserved3@ff600000 {
                    reg = <0x00 0xff600000 0x00 0x200000>;
                    no-map;
                    status = "okay";
            };
            reserved4@ff8a0000 {
                    reg = <0x00 0xff8a0000 0x00 0x12bf70>;
                    no-map;
                    status = "okay";
            };
            reserved5@ffbdfef0 {
                    reg = <0x00 0xffbdfef0 0x00 0x420110>;
                    no-map;
                    status = "okay";
            };

    };

};

The device_gen.h & platform_gen.yaml details as below

devices:

end: 0x50800000
start: 0x0
end: 0x50900000
start: 0x50810000
end: 0x85000000
start: 0x50a00000
end: 0xc0800000
start: 0xc0000000
end: 0xd0000100
start: 0xd0000000
end: 0x10000000000
start: 0xe5000000
memory:
end: 0xc0000000
start: 0x85000000
end: 0xd0000000
start: 0xc0800000
end: 0xe5000000
start: 0xd0000100

/* PHYSICAL MEMORY */

static const p_region_t BOOT_RODATA avail_p_regs = {

/* /memory@80000000 */

{

    .start = 0x85000000,

    .end   = 0xc0000000

},

/* /memory@80000000 */

{

    .start = 0xc0800000,

    .end   = 0xd0000000

},

/* /memory@80000000 */

{

    .start = 0xd0000100,

    .end   = 0xe5000000

},

};

While running i get the below error related to vaddr and page mapping as below, the debug log file

=> ext4load mmc 0:2 80000000 /home/root/sel4benchapp-image-arm-tpf-board
11543808 bytes read in 79 ms (139.4 MiB/s)
=> bootelf

Starting application at 0x85f69000 …

ELF-loader started on CPU: ARM Ltd. Cortex-A53 r0p4
paddr=[85f69000…86a461bf]
No DTB passed in from boot loader.
Looking for DTB in CPIO archive…found at 86079bf0.
Loaded DTB from 86079bf0.
paddr=[8523c000…85248fff]
ELF-loading image ‘kernel’ to 85000000
paddr=[85000000…8523bfff]
vaddr=[ffffff8085000000…ffffff808523bfff]
virt_entry=ffffff8085000000
ELF-loading image ‘sel4benchapp’ to 85249000
paddr=[85249000…85b71fff]
vaddr=[400000…d28fff]
virt_entry=455740
Enabling MMU and paging
Jumping to kernel-image entry point…

init_kernel

asm volatile(“tlbi vmalle1”) is commented and a macro from linux src is replaced … under debugging …
Bootstrapping kernel
available phys memory regions: 3
[85000000…c0000000]
[c0800000…d0000000]
[d0000100…e5000000]
reserved virt address space regions: 3
[ffffff8085000000…ffffff808523c000]
[ffffff808523c000…ffffff808524866b]
[ffffff8085249000…ffffff8085b72000]
asm volatile(“tlbi vmalle1”) is commented and a macro from linux src is replaced … under debugging …
Booting all finished, dropped to user space
ttbr0_el1 updated with 0x10000e4fd0000
ttbr0_el1 updated with 0x10000e4fd0000
ttbr0_el1 updated with 0x10000e4fd0000
ttbr0_el1 updated with 0x10000e4fd0000
ttbr0_el1 updated with 0x10000e4fd0000

 *sel4utils_new_pages_at_vaddr@vspace.c:492 Range for vaddr 0x10001000 with 1 4k pages not reserved!
 *sys_brk_dynamic@sys_morecore.c:161 Mapping new pages to extend brk region failed

seL4 Benchmark

Switching to a safer, bigger stack…
Setting up global fault handler…
ttbr0_el1 updated with 0x10000e4fd0000
ttbr0_el1 updated with 0x10000e4fd0000

kent-mcleod2 · February 27, 2025, 11:51am

It looks like your overlay file has 2 memory@80000000 node definitions when it should only have 1 with these values:

	memory@80000000 {
		device_type = "memory";
		reg = < 0x00 0x85000000 0x00 0x3b000000 >;
	};

Which should result in just this single entry under memory: in the platform_gen.yml file:

end: 0xc0000000
start: 0x85000000

Misbah · February 27, 2025, 1:55pm

I made the changes as suggested, but still the issue remains the same:

Output from platform_gen.yml & devices_gen.h:

devices:

end: 0x50800000

start: 0x0
end: 0x50900000

start: 0x50810000
end: 0x85000000

start: 0x50a00000
end: 0x10000000000

start: 0xc0000000

memory:

end: 0xc0000000

start: 0x85000000

/* PHYSICAL MEMORY */

static const p_region_t BOOT_RODATA avail_p_regs = {

/* /memory@80000000 */

{

    .start = 0x85000000,

    .end   = 0xc0000000

},

};

Debug output:

ELF-loader started on CPU: ARM Ltd. Cortex-A53 r0p4
paddr=[85f69000…86a441bf]
No DTB passed in from boot loader.
Looking for DTB in CPIO archive…found at 86078ab0.
Loaded DTB from 86078ab0.
paddr=[8523c000…85248fff]
ELF-loading image ‘kernel’ to 85000000
paddr=[85000000…8523bfff]
vaddr=[ffffff8085000000…ffffff808523bfff]
virt_entry=ffffff8085000000
ELF-loading image ‘sel4benchapp’ to 85249000
paddr=[85249000…85b71fff]
vaddr=[400000…d28fff]
virt_entry=455740
Enabling MMU and paging
Jumping to kernel-image entry point…

init_kernel

asm volatile(“tlbi vmalle1”) is commented and a macro from linux src is replaced … under debugging …
Bootstrapping kernel
available phys memory regions: 1
[85000000…c0000000]
reserved virt address space regions: 3
[ffffff8085000000…ffffff808523c000]
[ffffff808523c000…ffffff808524851f]
[ffffff8085249000…ffffff8085b72000]
asm volatile(“tlbi vmalle1”) is commented and a macro from linux src is replaced … under debugging …
Booting all finished, dropped to user space
ttbr0_el1 updated with 0x10000bffd0000

kent-mcleod2 · February 27, 2025, 7:52pm

Ok, now the issue shouldn’t be being caused by an incorrect memory map / load address.

Are you able to provide what NXP chipset model you are using?

When the elfloader starts, according to currentEL it is in EL1?

How do you know that the execution stops for a while? Does it take extra long for the first printf "ELF-loader started " or is it something else?

If you move your test for disabling the mmu so that it’s in between some of the initial elfloader prints, does the delay still occur to confirm that there is a multi-second delay contributed by the additional test directly, and not just indirectly because with the mmu disabled the early boot up takes longer to process crt0.s and enter main.

When your test is moved into main() and printf will be setup after initialise_devices() has been called, can you print out the initial value of sctlr_el1. If the mmu and caches are already enabled, then as indan said, you would need to clean them before disabliing the mmu.

Alternatively, from u-boot you can try using the icache and dcache commands to check the cache status and to manually flush and disable the caches before starting the elfloader.

Indan · February 28, 2025, 11:52am

The S32G3 is currently not supported by seL4. If you do want support, you have to do a proper seL4 port to it. That includes figuring out these SoC specific problems you are running into, we can’t help you with that as we don’t have the hardware.

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Issue with seL4 & ARMv8 config for MMU

Please find the output of the same as below:

Starting application at 0x85f69000 …

init_kernel

seL4 Benchmark

init_kernel

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